Publication date: 11 June 2009
Haliplex, an Australian producer of multi-service telecom infrastructure equipment for global markets, reckons to be saving over US$100,000 per year by exploiting the enhanced test and diagnostic capabilities of XJTAG boundary scan across its design, development and production activities.
Demands for miniaturisation of electronic products, whether for consumer or professional markets, show no signs of abating. From mobile phones to telecom-infrastructure equipment, customers have powerful reasons for seeking the highest product capabilities within the smallest possible outline. This is presenting tough challenges to electronic designers and product manufacturers.
Densely populated circuit boards with large numbers of components, including BGA-type packages with inaccessible I/Os, are difficult and time-consuming to test, whether the boards are first prototypes or production units. Verifying and debugging a prototype board can take days using traditional methods, and this can add significantly to the engineering costs to develop each new product. Then, when the board enters production, restrictions on access for in-circuit test probes can prevent contact with device I/Os and limit the test coverage that can be achieved.
Melbourne-based communication equipment producer Haliplex, which builds Multi-Service Provisioning Platform (MSPP) products that are the smallest of their kind and allow network designers to deploy traditional or next-generation services including Ethernet over bonded PDH circuits and Ethernet over SDH/SONET, has overcome these barriers to testing complex, densely populated assemblies. By adopting IEEE 1149.1 boundary scan testing in its development labs, and also by working with its contract-manufacturing partner to test production models using boundary scan, the company calculates it is saving over US$100,000 every year.
Anthony Merry, Chief Technical Officer at Haliplex, explains. “We have reduced the typical time to commission a new design by around four days. Given the number of new boards we develop in a year, this saves us around US$24,000 of engineers’ time.
“In production, the superior diagnostic capabilities of our boundary scan test system allow our manufacturing partner to identify and repair faults themselves, rather than adding them to our ‘repair pile’. As a result, the number of failed boards sent to us has reduced by around 90%. This is saving over US$64,000 of waste per year as well as around US$12,000 of our repair technicians’ time.”
Boundary scan uses dedicated test circuitry implemented on-chip in many components - particularly microcontrollers or FPGAs. Each device provides its own test access port, which is connected to a serial boundary-scan chain at the board level leading to a single four-pin header at the board edge. The test equipment is connected to the header, and no access to individual component I/Os is required.
This test technique, first proposed by the Joint Test Action Group (JTAG), was ratified as the standard IEEE 1149.1 in 1990. The XJTAG test system maximises the potential for boundary scan testing, by including features to streamline test generation and promote test re-use, and by taking advantage of available board-level connections including I2C or SPI buses to test non-JTAG components not directly connected to the boundary-scan chain. This now allows a wide range of components such as memories, Ethernet ports, ADCs and DACs to be tested from within the boundary scan environment. Other devices such as sensors, display drivers and switches are also all within reach.
Further enhancements include greater ease of use, thanks to GUI-based capabilities that help engineers to visualise the boundary scan chain and device pins, and maximise test coverage without having to manipulate the boundary-scan chain manually. A high-level test-description language also aids rapid test development and allows designers to re-use tests written for individual devices in subsequent designs, thereby delivering ongoing savings in engineering time.
“Our engineers are able to create tests for specific functions or areas of the board quickly and confidently,” comments Haliplex’s Anthony Merry. “We can see clearly how each test is operating and assess test coverage accurately.” The high-level test language makes it especially easy to build modular tests and optimise test coverage. Engineers can also begin testing new boards quickly by capturing the boundary scan chain for each new assembly automatically. Automatic connection tests are another valuable embedded capability. These reduce the task of verifying new prototypes, which can take over a day for some designs, to a matter of hours or even minutes. These enhancements to JTAG boundary-scan test are the foundation for Haliplex’s dramatic savings in engineering time when developing new products.
The production boards are built by a subcontractor, which is testing each unit using a run-time version of the boundary scan system optimised for production-test duties. The system’s diagnostic features enable the manufacturer to track down faults quickly so that repairs can be carried out directly. This enables the dramatic savings that Haliplex is achieving in terms of scrap and repair technicians’ time.
The run-time system delivers a cost-effective solution for executing pre-developed boundary-scan tests in a production environment. The manufacturer is also able to use the system to program devices and load serial numbers efficiently at the time of manufacture. “Our extended boundary scan capabilities have enabled an efficient, unified test strategy, reusing many of the tests devised during product development to test our production units.”
Merry sums up, “With the savings we have achieved by using the enhanced power of XJTAG boundary scan throughout development and production, our investment has paid for itself extremely quickly.”
For further information, visit: http://www.xjtag.com
